Beacon coders



July 22, 1.958 M. wlNlcK BEACON CopERs Filed oct. ze.' 195s Ammann ...MEN

- putbus t produce the code' Y BEACON coDEns Morris Winick, deceased, lateV ol' Belmont, Mass., by,

Martha R. Winick, administratrix, Belmont, Mass., as-

sguor to AmericauMachine 9al Foundry Company, a corporation of New Jersey Application )octoberr 26,1953, serial No. 388,562 1 1 Claims. (C1. 3403s4) This invention relates to beacon coders and has as an object the reduction of the number ofvacuum tubes and of the stand-by power supplies used in beacon coders.

Radar beacons are widely usedV for the recognition of objects. Forexample, the IFF system sends a pulse ch-allenge signal from a'station to an airplane or ship' within its range, and equipment on alfriendly airplane or ship receives the challengeand automatically transmits a signal in the form of a prearranged code to the station.

Beacons are -als'o used to accepteradar signals. from an approachingairplane and ,then to radiate a coded signal whichindicate's to the airplane navigation aid in the formV off` range and direction. Beacons'are alsocontemplated for the handling of airplnae landings atcongestedgairports; Uponreceip't of an interrogating pulse, abeacon Vcoder provides aV series of pulses at its output, each of which,v

causes the-beacon to transmit'ai'pulse@ The'intervalbelV tween-,successive pulses'rnay be shortte. YgrlS, microseconds) orfit Ymay kbe long (30 microseconds). 'The first outputfpulsev appearsgshortly' afterfas the interrogating pulses and is calledlthe ranging pulse; since'its transmis,-

sion bythe beacon'rprovidesv range information to theinf terrogatotn-v-Whenthe long interval'is Vtogbe twice theY duration, of the shortV interval, it is -possible toahieve separated in time by thelshort interval andthen selecting only those pulses that c onstituteLthe code. ;-'1`he first pulse appears shortlyv after the interrogatingpulse. In order to," preventV interference with f the operation .of .thecoder provision must be madeatodesensitize theeinput ofthe coder from-the time/'an interrogatingpulse is received ntilithe entire code lis transniittedf- Pn'er .be'aeen' cedere have been 'e1eetrenie, @praying chains of regenerative trigger circuitsv arranged Yin tandem and s'oconnected that onejwill tire the next in order after afpfredeter'mined delay. This delay may-be, e itherf shrt Y orlongand is deterir'iine'd by a switchthatjs part' of each stage.' l The trigger circuits aref connected tolan outputbus.

Thus if afchain is'Y activated'by. applying a'trigger toits input, a pulse willQstep., down'the' line, energizing 'the' ,Suchtpriorlcodersvhave vinforderto prevent interferencev United States Patent 0 `thezdesiredjresult by. generating a. train ofpulses equally` i cores 'andanother'line jof temporary .storagecores If vibratorsfanddiodes k precedingfthemgior providing gates havnasrtcr. durations than the kCodes; Standbyrower' vfotvlshl gat@ circuit isrrequiresi usuallyifgr th.r` f,,1a` mentsand one plate circuit, Each trigger circuito f s u c. h l 'prior' coders has included a one-shotV multivibratorfin eluding at A'least' anual-triode tube, requiring standby power for its filament andthe plate'oftheconducting separate 'trigger circuit is required'ifor 'every/. digitin aV code 'sol that when large numbers of digits' are Ainvolved correspondingly largenunibers Vof vacuuniltubes( arereiliefd-A V 15' .1 '.:fInf general, the number of unique codes desired ferenairborne oriportable beacongfarexceeds thenumber, de sir'ed inv iixedbeacons which-'areluse'dias aids `to naviga'` erenceY toe Y tion. As a result, simplen-.l smaller and .lighter coders et:

r. CC

than previously have been provided are needed. i in;

circuit is replaced by a pulse operated magnetic binaryswitch. Y

In the embodiment of the invention described herein, a magnetic binary is used for a switch at the Ventrance. to the coder; a first magnetic binary shift register is used to store the code symbol; a second magnetic binaryshift register is `used to recycle the shift pulse generator, to close the magnetic binary switch and to reset the first magnetic binary shift register after the code has, beenV delivered from it, and the shift pulse' generator uses two magnetic binaries and two vacuum tubesto deliverV shift pulses to the twoV shift registers.

V`Magnetic binary shift registers and the magnetiebinaries Ausedetherein are fully described in. an article byY An Wang vand Way Dong Woo published on pages 549-54 of volume 2.1, the January-1950 issue, of theV lournallof AppliedPhysics. WIt isv believed', therefore,i that it-"isV not .necessary in the`p`resentY disclosure, to give more thanthe following brief description of magnetic binaries: and shiftregisters employingsame.; i'

A magneticbinary core iscapable of beingmagn'etizedf to saturation in either ofv two` Adirectionski'Two states are said to arise from theY two',directionsApositive lor'.

active .state in whichtheA direction "of retentivity 'STDPPOQ siteto that which would result from theapplicatio'n ofia sensing or. shift pulse to' a shift winding Von.` the'core;

and a negative, or inactive state in whichzthe direction ofy retentivity is the Vsamefas" th'a.t which 'would 'resultfrrn the'applicationof a shift pulse. `Whenapplied to ancoreY in the' active state, la' shift'curjrent pulse causes` theinac-l tivefstate to-appear.. VWhen appliedto acore already inVV the inactive state,-a`shift pulse causesV no change instaten -A core inthe active, Vor positivev state, Vissaid to contain' a,bin ary`digit;one, and 'a core infthe negativejror inactive' state,`isr saidto contain the digit; zero.1"; `When acore,s,ll1vifts V from one state to another, avoltagefis'in-Q ducedinall of thewindingson it. AV shift currentjpulse willV have -no substantial effectgon'a core in an inactive state and substantiallynowvoltage'should be induced infitswindingsf. ;Y i 'y' magnetic binary/shift register has aline of storage a one signal is stored in the rst storage core,'the apfy pliation of' a shift pulse to the line otstorage cores will shift out the information Vstored. in the storage cores;v and will cause'the one tobe transferred to theirst core e The application ofja.

in the temporary storage line; shift pulse to-the temporary storage line :willausethe onef tofbe Vtransferred tothe second core jinv ,thegstorp-' ageeline.- .-Onej cycle ofgoperation'thusv consists of pulsing 1 'l-g f i'irst'the storage line and then the temporary V,storage f1 A tthe Vend of a cycle,-a one'l1as-aclvanced` one stage,1 .The presentinvention will. now Ybe described `withirefone'embodiment of the invention. y. if

The pulse source 10, whichrnay be a radar receiver,

connected to the input winding 11 of the mag-netic binary core 12`which serves as ;afmagnetic;.binaryswitchzf .The

outputwinding V13 of the "core`12' is'fconnectedliniseriesi with Vthe yrectifier ,9, Vtothegshift Winding'114 'fthejbinaryf core 16 of :fag shift pulse; generatorwhich supplies@ shift? PetentedJaly 2 2, 195sV l edrawing whichY Y isV a circuit e schematic on v 3 current pulses for the two shift registers to be described. The core 12 has a reset winding 18 connected to ground, and by the wire 19 to the winding 60 of core I, the other side of winding 60 being connected to the contacts of the switch 22 associated with the binary core H'of shift register No. 1.

The `core 16 has a feed-back winding 20 connected to the control grid of the triode 21 and to C (negative bias). The anode of the triode 21 is connected in series with the winding 22 of the core 16 and the winding 23 of the core 17 to the shift bus X. The core 16 also has a winding 24 connected to ground and through the wire 26 to a conventional delay line 27, which, in turn, is connected by the wire 28 to the winding 29 of the core J of the shift register No. 2. The delay line may be of the type disclosed on page 150 of Principles of Radar, third edition, published by McGraw-Hill Book Company.

The core 17 has a feedback winding 30 connected to the control grid of the triode 32 and to -C. The anode of the triode 32 is connected in series with the winding 31 of the core 17 and the winding 25 of the core 16 to the shift bus Y.

The shift register No. 1 includes eight stages comprising the eight binary storage cores A-H, the eight temporary storage cores AH', and includes the output core I. The shift register No. 2 includes nine stages comprising the nine storage cores J-R and the nine temporary storage cores J'-R. The cores A-R have the shift windings 34 :connected in series to the shift bus X. The cores AR have the shift windings 35 connected in series to shift bus Y. The outer ends of the shift buses are connected together at 36 and to B+ (anode voltage source). The cores J and R are the first and last-respectively, cores in series order of the second register.

The transmitting windings 37 of the cores A-I-I and J-R are connected through the rectiers 38 to the receiving windings 39 of the cores AH and J The transmitting windings 40 of the cores AH and I'Q -are connected through the rectifiers 41 to the receiving windings 42 of the cores B-I and K-R.

The receiving windings 45 of the cores A-H are connected to the blades of the double-pole, double-throw switches 22. One end of the line of interconnected contacts of the switches at the switch of core A is connected to the wire 46 which is connected through the rectifier 47 to one end of the winding 48 of the core R', the other end of ythe winding 48 being connected to ground. The outer contacts of the switches are connected together and in series with the inner contacts of the succeeding switch, the switch associated with core A being rst in order. When any switch is thrown in one direction, a reset pulse from the winding 48 having one sense will be delivered to the winding 45 of its associated core. When any of the switches 22 is thrown in the other direction a pulse having the opposite sense will be delivered to the winding of its associated core 45.

The output windings 29 on the cores I-Q are connected in series with the rectifier 58 to ground and through the previously described wires 28 and 26 and delay line 27 to the winding 24 of the core 16.

One side of the transmitting winding S on the core R is connected to ground, the other side being connected through the wires 57 and rectifier 25 to the winding 52 on the core J.

The receiving winding 53 on the core I is connected through the rectifier 54 to ground, and to the output terminal of the coder. The output terminal is connected to ground through a resistor 55.

Operation In the stand-by condition, core 12 would be active with respect to pulses from the pulse source 10. Core 16 would be active with respect to pulses received from Winding 13 of core 12. Core 17 wouldbe activewith respect 4 to pulses on winding 23 received when tube 21 is red. Triode 21 is biased beyond cutoff. Triode 32 is biased slightly above cutoff. Cores AR are inactive with respect to current pulses in shift -bus Y. Core J is active with respect to current pulses in shift bus X. Cores K-R are inactive with respect to current pulses in shift bus X.

A live digit code in which the first two spaces are long and the last two spaces are short will be used as an illustration of the operation of the circuit. For this code, it is desired that cores G, E, D and C shall be active with respect to pulses on shift bus X after a reset pulse is received on wire 46. The Iswitch blades connected to the windings 45 on these cores are therefore thrown to the right. The switch blades connected to the windings 45 on cores H, F, B and A are thrown to the left thus making these cores inactive to current pulses in shift bus X after a reset pulse is received on wire 46. Core I contains the ranging pulse and is permanently wired so as to be active with respect to shift bus X after a reset pulse is received on wire 4,6..

To start the code, an initiating pulse is received from the pulse source 10 -through the winding `11 causing core 12 to change its state. Core 12 is thereafter inactive with respect to pulses received from the pulse source 10 until a reset pulse causes a current pulse to go through winding 18. The change of state of core 12 causes a voltage to be induced in winding 13 and a current pulse goes through winding 14 of core 16 `causing it to start changing its state. The flux change will cause a voltage to be induced in the grid winding 20 that causes triode 21 to start conducting. The flow of plate current from triode 21 in winding 22 will initiate regenerative action through Winding 20, and the grid potential as well as the plate current will increase rapidly to equilibrium value. The plate current through the winding 22 will cause the core 16 to switch from its active state to its inactive state following which the triode 21 will cease firing since grid voltage will be no longer induced in grid winding 20. The plate current pulse from triode 21 ows through windings 22 on core 16, 23 on core 17 and then through all the windings 34 o n cores A-R and at'36 goes to B+. This constitutes a pulse in shift bus X. The active cores A, I, G, E, D and C will be rendered inactive by the shift pulse and at the same time a pulse willbe generated in each transmitting winding of the cores G, E, D and C and will pass through the receiving windings 39 of cores G', E', D' and C' of the temporary storage line, placing these temporary storage cores in the active state with respect to a shift pulse to .be supplied through the shift windings 35 from the shift bus Y. As core I is rendered inactive by the current pulse in shift bus X it causes a voltage to be induced across winding 53 and a current pulse flows through crystal dioder54 and the output resistor 55. The causes a voltage pulse to appear at the output and constitutes the ranging pulse of the code. At the same time the one stored in core J will be shifted by the action of the current pulse into core J', core I becoming inactive.

When the triode 21 of the shift pulse generator fires and draws plate current, the core 17 will be switched to its maximum saturation value by the current through its winding 23. After triode 21 has fired and gone out, the condition of core 17 returns from its maximum saturation value `to its maximum residual value, thus generating a pulse across winding 30 of the proper polarity to fire triode 32. When triode 32 fires, its anode current flows through windings 31 of core 17, 25 of core 16 and then through shift bus Y through windings 35 on cores A-H and J'-R; This causes temporary storage cores G', E', D and C' to become inactive, thereby causing pulses to be generated in windings 40 of these cores and through the rectiers 41 to receiving windings 42 on cores H, F, E and D. 'At the same time the current in Winding 25 causes core 16 to return to an active state with respect to windings 14 and 24. A 4

vided for the device to operate.

' respect to pulses from the pulse source.

'At the same time thecurrent pulse in shift bus Y causes core Ifto become inactive and throughjtransmitting Winding40 and receiving winding 42, causes core K to become active. The induced voltage in jwinding 2 9 of core If vpulse as receivedfby core 16 on winding 14. Y Voltages induced in thev windings 29 ofrjcoresKr'- act/during theosecond-ninth `cycles of operation to ,cause triodes Y2711-3210 ,conduct for producvins'shift pulses During the second cycle of operation, the onesi present in cores H, F, E and D of shift register 1 are advanced to. cores 1,:G,.F and E respectively, but no output appears. The -.one in core K of shift register 2 is advancedto core L During the thirdfcycle of operation, theA ,onespr` esent incores'I-I, F, E and D of shift registerj 1 are advanced to the'output'clorel and torcores G,- F andME'respectively: --The -o`ne incore L of shift register 2 is advanced to core M.V The oneV in the output core I appears at the output. During the fourth cycle of operation the ones present in cores G, F and E of shift register 1 are advanced to cores H, G and F, respectively. The one in core M of shift register 2 is advanced to core N. During the fifth cycle, the ones in cores H, G and F of shift register 1 are advanced to the output core I and cores H and G respectively. The one in core N of shift register 2 is advanced to core O. During the sixth cycle, the one in core H is advanced to the output core I and the one in core G is advanced to core H. The one in core I appears at the output. The one in core O of shift register 2 is advanced to core P. During the seventh cycle of the one in core H is advanced to the output core I and the one in core P is advanced to core Q. lDuring the eighth cycle shift register 1 is inactive and the one in core- Q of shift register 2 is advanced to core R The one in core I appears at the output. During the ninth cycle the one in core Q is advanced to core VR'. ANo five digit code of the type described can require more than 9 cycles to be read out, thus adequate time has been pro- During the Atenth cycle the one in core R is advanced to core J. Core R is not linked by a winding 29 as are cores I-Q', therefore no pulse is fed into delay line 27 and at the'end of the tenth cycle there is no current pulse through winding 24 of core 16. Thus no further cycles of operation will occur from the action of the coder. However during the tenth cycle when core R is changed to the inactive Ystate by the operation of shift bus Y, 'a reset pulse is induced across winding 48 of core R and a current pulse vis caused to flow through rectifier 47, wire 46, then ground. This current pulse sets ones in cores I, G,

E, D and C and returns core 12 to its active state with The coder is now completely reset and delivers the desired ve pulse code at its output when it receives the next initiating pulse.

More or fewer binaries can be used to provide different codes. The size of the two tubes in the shift pulse register will depend upon the number of cores used but regardless of the number of cores, only two tubes are required.

While one embodiment of the invention has been described for the purpose of illustration, it should be understood that the invention is not limited to the exact v apparatus and circuit illustrated as modifications thereof may be suggested bythose skilled in theY art vwithout departure from the essence of the invention. 1 Y

What is claimed is: V

1. A coder comprising a first v register having a plurality'of'stages, a second. magnetic binary shift register having an equal plurality of stages plus an additional stage, means for cycling said registers for shifting al code stored in said rstregister out of Ysaid rst register, and for shifting a one stored in the iirst stage of said second register through saidV second register, said means including a shift pulseV generator, a signal source connected to saidV generator, means actuated by a signal from said source for causing s'aidf'generator` to cycle said registers twice only, means connecting all of said stages of said second register with said generator except the last stage in order of said second register for supplying signals to said means of said generator for causing said generator to continue to cycle said registers, and means includingV switches conecting said last stage of said second register with all of the stages of said iirst register for resetting the code in said rst register.

2, A coder as claimedin claim 1 in which'switchin'g means connects the signal source and generatorA and includes meansV actuated'by the passage of a signal from said source to saidV generator 'for' preventing another sig# nal from said source from passing to said generator, and

in which means connecting said switching means and Y said last stage of said second register supplies a signal 'pulse to said switching means when said last stage has been cycled to shift said one therefrom, said switching means including means actuated by said signal pulse for causing said switching means to be in condition for passregister, and having a plurality of temporary storage cores Y one more in number than saidV temporary storage cores of said rst register, shift windings on said cores, a shift pulse generator connected to said shift windings for shifting the ones through the cores of said iirst register and for shifting a one in the rst storage core of said second register through the cores of said second register to the last temporary storage core in series order of saidsecond register, an output winding on said last temporary storage core of said second register, and means including v receiving windings on said storage coresof said first register, and switches connected to said last mentioned windings and to said output windingV on said last. core of said second register for reinserting a code in the storage cores of said rst register.

4. A coder as claimed in claim 3 in which a Ysignal source is connected to said generator, said generator including means using a signal from said source to ener-` gize said generator to supply a single shift pulse togsaid storage cores and then to supply a single shift pulse to said temporary storage cores, in Vwhich switch means is` switch means to again pass a signal from said source toY said generator. p Y

5. A coder as claimed'in claim 4 in which the switch means is a magnetic binary core having an output wind- 1 ing connected to said'rgenerator, and having input windings connected to said source and to said output winding on said last core of said second register.

magnetic binary shift i 6. A coder as claimed in claim 5 in which other output windings are provided on a'll of said temporary storage cores of said second register except said last core thereof and which are connected to said generator to supply signals thereto for energizing said generator to supply shift pulses to said shift windings.

7. A coder as claimed in claim 3 in which other output windings are provided on all of said temporary storage cores of said second register except said last core thereof and which are connected to said generator to supply signals thereto for energizing said generator to supply shift pulses to said shift windings.

8. A coder as claimed in claim 7 in which a signal source is connected to said generator, said generator including means using a signa1 from said source to energize said generator to supply a single shift pulse to said shift windings on said storage cores vand then to supply a single shift pulse to said temporary storage cores, in which switch means is connected between said source and said generator and is actuated by the passage of a signal from said source to prevent the passage of another signa1 from said source to said generator, and in which said output winding on said last core of said second register is connected to said switch means.

9. A coder as claimed in claim 3 in which other output windings are provided on all of said temporary storage Vcores of said second register except said'last core thereof, in which a delay line is provided, and in which means including said'delay line is provided Ifor connecting the last mentioned windings to said generator yto supply signals thereto for energizing saidgenerator to supply shift pulses to said shift windings. g

10. A coder as claimed in claim 9 in which said last core of said second register has a transmitting winding thereon, and in which the first storage core of said second register has a receiving winding thereon connected to said last mentioned transmitting Winding.

l1. A coder as claimed in claim 3 in which said last core of said second register has a transmitting winding thereon, and in which the rst storage core of said second register has a receiving'windin'g thereon connected to said last mentioned winding.

References Cited in the tile of this patent UNITED STATES PATENTS 2,649,502 odeu Aug. 18, i952 2,654,080 Browne Sept. 29, 1953 2,729,807 Paivinen Jan. 3, 1956 

